Projects

Microelectronics Development Division Projects

Following are some of the ongoing projects currently progressing under Microelectronics Development Division.

VLSI & Embedded processor Design

Digital Programmable Hearing Aid

A project for development -Fabrication of ASIC (Application Specific Integrated Circuit) productionization of Digital Programmable Hearing Aid and its deployment is being implemented by CDAC, Thiruvananthapuram

An ASIC based Digital Programmable Hearing Aid has been designed & fabricated using130 nano-meter technology and is successfully tested for its functionality. Both Body worn and behind-the-ear type DPHAs have been developed using this ASIC. The Body Worn (BW) type DHPA is designed and tested for mild, moderate, severe and profound hearing losses and its environmental testing is completed as per IS:10775-1984. Field trials of BW Type has been conducted at All India Institute for Speech and Hearing Mysore, All India Institute of Medical Science Delhi, Ali Yavar Jung National Institute for Hearing Handicapped Mumbai, Christian Medical College Vellore etc. The Behind-the-ear (BTE) type Hearing Aid module is developed and its field trial is in progress. One patent application is filed for the technology developed under the project.

Low Power CODEC for Digitally Programmable Hearing Aids

A Low Power CODEC for Digitally Programmable Hearing Aids is being designed and developed by IIT Madras which would be used as a front end for Digital Programmable Hearing Aids. The complete integrated IC with all the blocks included have been designed, fabricated and packaged in a QFN32 package with the required pin configuration. After characterisation, the bugs have been removed and an improved design is being sent for fabrication. This IC will replace the imported IC being used in the Digital Programmable Hearing Aid being developed by CDAC

Study on Development of Microprocessor

The objective of the study is identification and interaction with institutions that can contribute and collaborate in the Microprocessor design and development activity, technical evaluation of various processor architecture implementations available today and preparation of a detailed proposal for setting up a resource centre for design and development of processors and IP cores and for the design, implementation including specifications of a Microprocessor device/family of devices with full ecosystem for application porting. A comprehensive approach for taking up a specific system implementation as an initial primary application would also be suggested in the study.

Processes

a. CMOS

Low Temperature Co-fired Ceramic (LTCC) Facilities

Development of Advanced Processing Capabilities in LTCC is being jointly supported by NPMASS-DRDO and DeitY at C-MET Pune. Infrastructure is being created to handle the advanced applications in LTCC such as high density interconnects, microfluidics and micro-sensor packaging. This State-of-the-art facility being set up in the country would be used for strategic applications.

b. Micro Electro Mechanical Systems (MEMS)

MEMS based sensors

Development of Micro Electro Mechanical Systems (MEMS) based Integrated Micro Gas Sensor for sensing Volatile Organic Compounds (VOC) and Pollutant Gases like Benzene, Ethanol, Methane, Methanol and Propanol & Pollutant gases in the air is being implemented by CEERI Pilani. This would be taken up by developing 4 different sensing layers. The design of 4 independent heaters for 4 different sensing layers is also completed and the masks are ready for fabrication.

Deposition of Zinc Oxide, tungsten oxide (WOx), iron oxide (Fe2O3), and Titanium oxide (TiO2) sensing layers is completed. X-ray diffraction peak intensity for WOx, Fe2O3, and TiO2 films have been evaluated by X-ray and XPS methods. Development and testing of PRTs and microheaters is completed. Temperature creation and measurements were carried out on silicon substrates. A patent is being filed for the technique to measure the temperature on Silicon substrates. The evaluation of ZnO, Titanium Oxide and Iron Oxide sensing layers for electrical conductivity is completed.

Setting up of facilities for fabrication of MEMS devices at Tezpur University

Facilities for fabrication of MEMS is being set up to impart training to Ph. D. scholars, PG students from in-house i.e. the Tezpur University and researchers from nearby institutes and research organizations for fabrication of MEMS devices.

Analog Mixed Signal Circuit Design

(i) Centre for Analog Mixed Signal Integrated Circuit Design at IIT Madras

The focus of project is on setting up centre for design, Testing and Characterization of Ultra-High Speed data Communication and Data Conversion Analog Mixed Signal Integrated Circuit. The institute has also specialised in development of low power analog and mixed signal designs. Some of the designs carried out are:
  • Continuous-time Delta Sigma (DS) analog to digital converter incorporating the fast loop resulting in the highest sampling rate and the highest signal bandwidth reported thus far in a 180nm CMOS process
  • A 1Giga Sample per second DS ADC incorporating the assisted opamp technique
  • An 18 bit audio DS modulator fabricated in 180nm CMOS was designed, fabricated, and tested. The DAC architecture in the audio DS modulator meets the stringent noise requirements at the high resolution.
  • Efforts are ongoing to realize a memoryless DS modulator without internal reset.
3 (2 International + one Indian) patents have been filed under the project.

(ii) Centre for Analog Mixed Signal IntegratedCircuits at IISc Bangalore

The focus of project is on setting up centre for design, Testing and Characterization of analog and mixed signal ICs for Wireless Communication applications. Some of the designs carried out include:
  • Design of low power radio and adaptive radio Receiver and transmitter
  • Low power adaptive RF receiver chain for 802.15.4
  • Low power RF power amplifier (2.4GHz) for 802.15.4 and a frequency multiplication based PLL, incorporating a spur reduction technique
2 international and 4 Indian patents have been filed. Filing of 2 more international patents under progress

(iii) Design of Mixed Signal Circuits for Instrumentation Applications at CEERI, Pilani

Project focus is on design of Analog and Mixed ICs for Instrumentation Applications. 10 Bits SAR ADC and 10 bit DAC has been designed, fabricated, tested and characterised for use in pressure sensor electronic circuitry. Capabilities of designing circuits for conditioning and processing the sensor output (at present MEMS based pressure sensor) developed. Attempts are being made to design and fabricate MEMS and CMOS circuitry in a single chip.

(iv) Analog Mixed Signal and RF IC development and Test for Biomedical Applications at IIT Bombay.

The project aims at development of expertise in the design and testing of analog, mixed signal & RF ICs for bio-medical applications. 3 ICs dedicated for bio-medical applications would be designed, fabricated and tested under the project viz.
  • General-purpose Low-power analog signal conditioning chip for portable and personal health-care monitoring applications.
  • Low-power analog ECG signal conditioning chip with on-chip wireless connectivity for remote health care.
  • Low-power pulse oximetry, bio-sensor analog signal conditioning and modulation and bio telemetry test chip.
IIT Bombay has completed design of a reference generators and drivers, ECG instrumentation amplifier and Operational amplifiers. The chips are being sent for fabrication.

(v) Design and Implementation of Low Power Analog front end Modules for wireless Sensor Networks

Design of LNA and mixer completed and implemented in 180nm technology and their performance was compared with those in the literature.

Modeling & simulation CAD tool

Thermal aware testing of VLSI circuits and systems

Strategies are to be developed for ensuring low temperature during VLSI circuit testing and thermal aware scheduling for testing System-on-Chip (SoC) and Network-on-Chip (NoC) designs under the project. Thermal aware reordering of test vectors for Thermal aware Automated Test Pattern Generator (ATPG) design, don' t care filling and Network-on-Chip testing is completed